Capacity increases are accelerating for nonvolatile semiconductor memory devices typified by NAND flash memory. When memory cells are shrunk to increase capacity, inter-layer insulating films between the memory cells become thin and leak current increases. In the case of a planar memory cell, the coupling ratio decreases between the control gate and the floating gate. Therefore, programming data to the memory cell is insufficient; and shifting to high threshold values is particularly difficult. In particular, in the case of multi-bit memory cells, the maximum value of the threshold voltage cannot be kept within a constant level to improve the controllability; and the problems of insufficient shifting to the high threshold values recited above worsen.
Technology is discussed in JP-A 2001-126490 (Kokai) to increase speed and reliability by performing sequential programming from a state near an erase state after shifting to the threshold value furthest from the erase state in a multi-bit memory.
Further, technology is discussed in JP-A 2007-305204 (Kokai) to reduce capacitance coupling noise by performing a weak programming after the erasing operation and subsequently performing multi-level programming operations to raise the lower limit value of the threshold distribution of the erase state and amounts of threshold shifting is smaller in programming operations.
Even in the case where such methods are used, insufficient shifting to high threshold values is not improved sufficiently; and there is room for improvement.